AI 与机器学习2024arxiv.org
大语言模型硬件加速:综述与比较
Hardware Acceleration of LLMs: A comprehensive survey and comparison
进阶 · 约 90 分钟读完前置知识:计算机体系结构基础、LLM 推理流程、半导体工艺节点概念
导读
这是一篇综述,系统梳理并比较了用于大语言模型推理/训练的各类硬件加速方案(如 GPU、ASIC、FPGA、存内计算等),并尝试把不同半导体工艺节点下的性能数据用拟合多项式外推到 16nm 这一共同基准,以便横向对比。
HN 关注点:LLM 性能瓶颈正从算力转向内存带宽(“内存墙”),以及为快速迭代的模型定制专用硬件是否划算。
HN 评论精选
这几条评论里:支持 1 补充 2
补充补充“内存墙”历史脉络,指出 LLM 瓶颈正转向内存带宽、存内计算是应对方向,并解释论文的 16nm 归一化方法。
这篇论文背景讲得太少,我补充一些:早在 90 年代就有人注意到 CPU 的 FLOPs 提升速度快于内存带宽。1995 年 William Wulf 和 Sally Mckee 预测这种分化会导致“内存墙”——多数计算会被数据访问而非算术运算卡住。过去 20 年,服务器峰值 FLOPS 每两年增长 3 倍,而 DRAM 带宽和互连带宽每两年只增长 1.6 倍和 1.4 倍。因此 LLM 的训练和推理瓶颈越来越偏向内存带宽,对自回归 Transformer 解码器来说尤其可能成为主导瓶颈。这催生了存内计算(CIM/PIM)这类新技术:直接在内存中的数据上做运算,而不是先把数据搬到 CPU 寄存器,从而改善延迟和功耗,或许能绕开“内存墙”。另外,为了在工艺尺寸不同的情况下比较 ASIC 和 FPGA,论文引用 Stillmaker 和 Baas 的 CMOS 性能缩放公式,把性能外推到 16nm 的共同基准。
refibrillator查看英文原文
This paper is light on background so I’ll offer some additional context: As early as the 90s it was observed that CPU speed (FLOPs) was improving faster than memory bandwidth. In 1995 William Wulf and Sally Mckee predicted this divergence would lead to a “memory wall”, where most computations would be bottlenecked by data access rather than arithmetic operations. Over the past 20 years peak server hardware FLOPS has been scaling at 3x every 2 years, outpacing the growth of DRAM and interconnect bandwidth, which have only scaled at 1.6 and 1.4 times every 2 years, respectively. Thus for training and inference of LLMs, the performance bottleneck is increasingly shifting toward memory bandwidth. Particularly for autoregressive Transformer decoder models, it can be the dominant bottleneck. This is driving the need for new tech like Compute-in-memory (CIM), also known as processing-in-memory (PIM). Hardware in which operations are performed directly on the data in memory, rather than transferring data to CPU registers first. Thereby improving latency and power consumption, and possibly sidestepping the great “memory wall”. Notably to compare ASIC and FPGA hardware across varying semiconductor process sizes, the paper uses a fitted polynomial to extrapolate to a common denominator of 16nm: > Based on the article by Aaron Stillmaker and B.Baas titled ”Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7nm,” we extrapolated the performance and the energy efficiency on a 16nm technology to make a fair comparison But extrapolation for CIM/PIM is not done because they claim: > As the in-memory accelerators the performance is not based only on the process technology, the extrapolation is performed only on the FPGA and ASIC accelerators where the process technology affects significantly the performance of the systems. Which strikes me as an odd claim at face value, but perhaps others here could offer further insight on that decision. Links below for further reading. https://arxiv.org/abs/2403.14123 https://en.m.wikipedia.org/wiki/In-memory_processing http://vcl.ece.ucdavis.edu/pubs/2017.02.VLSIintegration.TechScale/
补充追问“存内计算”到底指什么硬件形态。
我不太熟悉,这里的“in-memory”是指把 CPU 和 RAM 结合在一起的专用硬件吗?
yjftsjthsd-h查看英文原文
I'm unfamiliar; in this context is "in-memory" specialized hardware that combines CPU+RAM?
支持认为模型迭代太快,专用硬件投入容易打水漂。
存内计算看起来是正确方向,不仅因为性能,还因为为一个很可能几个月内就过时的模型去造 ASIC 或烧 FPGA 根本说不通。
moffkalast查看英文原文
In-memory sounds like the way to go not just in terms of performance, but in that it makes no sense to build an ASIC or program an FPGA for a model that will most likely be obsolete in a few months at best if you're lucky.
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